1. Field of the Invention
The present invention generally relates to signaling between electronic units. More specifically, the present invention relates to signaling on bidirectional signaling busses.
2. Description of the Related Art
Electronic systems generally comprise multiple electronic units that are interconnected by signaling conductors. These signaling conductors typically are electrically conducting paths made of copper, aluminum, or other such material.
The signaling conductors used in high speed electronic systems are known as transmission lines, defined by a characteristic impedance and a propagation velocity. The transmission line has distributed electrical properties of resistance, inductance, conductance, and capacitance per unit length that are constant along the transmission line. Typically, in transmission lines, resistance and conductance per unit length is small, so that high speed signal behavior on the transmission line is chiefly determined by the inductance and capacitance per unit length. High speed signaling behavior is seen when voltage risetimes and falltimes of signals is less than the time it takes for the transition to propagate from a first end of the transmission line to a second end. Examples of transmission lines are coaxial cables, twisted pairs, and wires at a constant distance from a reference plane (e.g., ground). For example, many transmission lines are signaling conductors on printed wiring boards (PWBs) in computer systems. Such transmission lines are commonly designed to have approximately 50 ohms characteristic impedance, with propagation velocity of about 65 pS (picoseconds) per centimeter.
A number of methods are used to transmit signals on transmission lines. For example, some electronic systems place terminating resistors at each end of each transmission line. If a signal is propagating along a 50 ohm transmission line and reaches an end of the transmission line which is terminated by a 50 ohm resistor, no reflection occurs. Such a termination technique dissipates a large amount of power. Reflections result from mismatches in impedances. For example, if a one volt signal edge propagating along a 50 ohm transmission line encounters an open circuit (i.e., very high impedance, typical of an unterminated receiver), a one volt reflection propagates backward along the transmission line, causing voltage on the transmission line following the reflection to be two volts. If the one volt signal should encounter a short circuit, a minus one volt reflection propagates backward along the transmission line.
A widely used alternative technique for driving signals on transmission lines is called source termination. Source termination uses a driver that has the same impedance as the transmission line. For example, such a driver could be thought of as a 50 ohm resistor coupled to the exemplary 50 ohm transmission line, the other end of the resistor being coupled to a supply voltage to drive a logical “1”, or to a ground voltage to drive a logical “0”. FIG. 1 shows an electronic system 100, comprising a first electronic unit 101, a second electronic unit 111, and a transmission line 120. First electronic unit 101 further comprises a driver 105 having inputs D and E for data and enable, respectively. Driver 105 is coupled to a first end 121 of transmission line 120. First electronic unit 101 further comprises a receiver 106 that receives a signal from the first end of transmission line 120 and drives a signal 104. Similarly, second electronic unit 111 comprises a driver 115 and a receiver 116. First and second electronic units 101 and 111 time multiplex their use of transmission line 120; that is, they take turns driving and receiving signals over transmission line 120. Various protocols are known to assign ownership for driving (i.e., electronic unit 101 or electronic unit 111) of the signaling conductor at any point in time.
FIG. 2 shows a conventional source terminated driver 200 as an embodiment of drivers 105 and 115. If transmission line 120 is a 50 ohm transmission line, driver 200 should have an impedance of 50 ohms when driving either a logical “1” or a logical “0” in order to match the transmission line. Note that some tolerance is allowable in the matching of a source terminated driver and the transmission line and signals can still be transmitted reliably. Actual degree of mismatch is dependent on noise and other factors. Typically, if the impedance of the source terminated driver is within 20% of the characteristic impedance of the transmission line, signaling on the transmission line will be acceptable. For exemplary purposes here, a perfect match is assumed for simplicity. Driver 200 is designed such that the impedance of p-channel field effect transistor (PFET) QP1 (when QP1 is conducting) plus the value of resistor R1 is 50 ohms. Similarly, the impedance of n-channel field effect transistor QN1 (when QN1 is conducting) plus the value of resistor R1 is 50 ohms. When the signal coupled to input “E” is “1” and the signal coupled to input “D” is “1”, QP1 conducts and QN1 is turned off. Output “OUT” is driven high with an impedance of 50 ohms. When “E” is at “1” and “D” is at “0”, QP1 is turned off, and QN1 conducts, driving output “OUT” low with an impedance of 50 ohms. When input “E” is “0”, both QP1 and QN1 are turned off and the impedance of driver 200 seen at “OUT” is very high, that is, the impedance is at least an order of magnitude higher than the characteristic impedance of the transmission line, and, typically, is over a megohm. NAND 201 has an output that drives the gate of QP1 active (i.e., a low voltage to turn on QP1) if both the signal coupled to input “D” and the input coupled to “E” are “1”. NOR 202 has an output that drives the gate of QN1 active (i.e., a high voltage to turn on QN1) if the signal coupled to input “D” is “0” and the signal coupled to input “E” is “1”.
FIG. 3 shows voltage waveforms as seen at nodes 121 and 122 as driver 105 (see FIG. 1) drives a “1”. The length of transmission line 120 has a total propagation delay of “Tprop”; that is, a signal takes “Tprop” time to propagate from node 121 to node 122. For example, if transmission line 120 has a propagation velocity of 65 pS per centimeter, and is 100 centimeters long, Tprop would be 6500 pS. VNE is the voltage at the “near end”, that is, near or at the driver, in the present example, at node 121. Since transmission line 120 in the example has a characteristic impedance of 50 ohms and driver 105 has an impedance of 50 ohms, a signal having half the voltage applied to a source of QP1 propagates down transmission line 120. After one “Tprop” time, the signal reaches node 122, the “far end” of transmission line 120. Driver 115 is disabled (i.e., a signal at node 113 is “0”) at this time, so driver 115 has a very high impedance. Receivers 106 and 116 also are designed to have very high impedance. As discussed earlier, as the signal encounters a very high impedance, a doubling of the voltage occurs and propagates backwards along transmission line 120. For discussion, Vdd is the voltage applied to the source of QP1. VFE, the voltage at note 122 becomes equal to Vdd as the signal reaches node 122. In practice, finite voltage risetimes and a need to charge parasitic capacitance associated with physical elements (e.g., module pins and other connectors) cause VFE to not double “instantly”. In addition, tolerances in driver 105 and transmission line 120 may cause the “doubled” voltage at node 122 to be slightly higher or slightly lower than Vdd. Still referring to FIG. 3, when the reflection returns to driver 105 after two “Tprop” times, the voltage at node 121 becomes Vdd. As before, tolerances may make the voltage at node 121 slightly different than Vdd (in the case of a rising signal); however in a properly designed electronic system such differences are small. Until the reflection returns, driver 105 drives a current equal to Vdd/(100 ohms). (Impedance of (QP1+R1)=50 ohms, and the characteristic impedance of transmission line 120 is 50 ohms.) When the reflection returns, voltage at node 121 rises to Vdd, causing current in driver 105 to stop flowing. A similar process occurs when driver 105 drives a “0”.
FIG. 3 shows “Tbit”, the shortest time needed before driver 115 could electrically drive a signal after driver 105 has driven a signal. Note that Tbit is shown to include a small time following when VFE (i.e., voltage at node 122) has reached “1” (i.e., Vdd). This small time is the time needed for receiver 116 to propagate the signal via signal conductor 114 into a latch and for other circuitry to enable driver 115 via a signal on signal conductor 113. In modern high speed systems, this time is small compared to typical Tprop times. In subsequent discussion, for simplicity, this time is assumed negligible.
A problem exists, however, in enabling driver 115 to drive a signal immediately upon receipt of the signal from driver 105. Driver 105 must be disabled before the signal driven by driver 115 arrives at node 121 (FIG. 1), but after the reflection of the signal driven by driver 105 has returned to node 121. A system designer must know how long Tprop is for all such transmission lines, and must also know where clock edges are in his or her timing diagrams. Two approaches have been used to provide for resolution of the problem. A first approach, seen in FIG. 4A, uses a “dead cycle”. A dead cycle is a bus cycle (a “Tbit” time) in which a signaling conductor, (i.e., a transmission line) is not driven by any driver coupled to the signaling conductor. That is, all drivers coupled to the signaling conductor are switched to a high impedance state (“high impedance” meaning at least an order of magnitude higher impedance than the characteristic impedance of the transmission line). “A drives” represents the time when driver 105 of FIG. 1 is enabled; “B drives” represents the time when driver 115 is enabled. EN-A, which is the signal at the “E” input of driver 105, rises at 407 to enable driver 105. At 408, EN-A falls, disabling driver 105. During “Tbit 1”, driver 105 drives a “1”, with rise 401 going from zero volts to Vdd/2 as described earlier. After one Tprop time, rise 402 occurs at node 122, and at the end of the “Tbit 1” time, driver 105 is disabled (i.e., switched to a high impedance state). Driver 105 had been sourcing a current equal to Vdd/(100 ohms); disabling causes Driver 105 to quickly stop sourcing current, causing the voltage at node 121 to fall at point 403. Voltage at points on transmission line 120 will, in practice, rise and fall according to standard behavior of a transmission line having a very high impedance at both ends. Points 404 and 405 simply indicate that the voltage at node 121 can become a complex waveform dependent on small capacitance parasitic or other parasitic factors. The signal waveform is not drawn following point 405 because the waveform quickly becomes hard to predict, in general. Similarly the reflection of the fall at point 403 is seen at node 122 after a Tprop delay. EN-B represents the signal on node 113 of FIG. 1, that is, at input “E” of driver 115. EN-B rises at 409, at the beginning of “Tbit 3” time. Using a dead cycle ensures that driver 105 is not enabled when a signal driven by driver 115 arrives, but “Tbit 2” is totally wasted, having no data transmitted by either driver 105 or driver 115.
Another solution to the problem described is to use a “live cycle”, as shown in FIG. 4B. A live cycle is a bus cycle (a “Tbit” time) when the last driver to drive a signal during a “Tbit” time continues to drive the same logic level. Again, the time during “Tbit 2” is wasted. During the live cycle scheme, driver 105 is kept enabled during “Tbit 2”, and the “D” input of driver 105 is kept the same as was applied during “Tbit 1”. EN-A rises at 427, the start of “Tbit 1” and does not fall until 428, the end of Tbit 2. EN-B rises at 429, the start of Tbit 3. Voltage at node 121 rises to Vdd/2 at 421. Voltage at node 122 rises to Vdd at 422 after a Tprop delay. The reflected signal returns to node 121 at 423, causing current in driver 105 to stop flowing, as discussed earlier. When EN-A disables driver 105 at 428, no “glitch”, as was seen at 403 in FIG. 4A, occurs, since no current was flowing in driver 105 at 428. EN-B rising at 428 enables driver 115, causing voltage at node 122 to fall from Vdd to Vdd/2 at 424. Driver 115's signal arrives at node 121 at 425, and driver 115's signal reflection returns to driver 115 at 426. As with the dead cycle scheme, “Tbit 2” is used only to ensure that neither driver 105 nor 115 is conducting when the other's signal arrives.
Driver 105 or driver 115 (if properly designed to always match the impedance of transmission line 120) can drive a series of signals, during which the other driver is disabled, because reflections are suppressed by the proper termination at the source (i.e., the driver).
Therefore, a need exists to provide method and apparatus that allow a first driver at a first end of a transmission line to drive a signal during a first time period, followed by a second driver at a second end of a transmission line to drive a signal during a second time period, without a dead cycle or a live cycle between the first time period and the second time period.